A typical dynamic random access memory (DRAM) cell includes a metal-oxide-semiconductor field effect transistor (MOSFET) and a capacitor. The MOSFET is used as a pass transistor to allow charge to be transferred to and from a capacitor used to store data.
Memory devices, such as random access memories (RAMs) and read only memories (ROMs) access single entries according to applied addresses, however, other types of memory devices can provide a matching function with respect to all entries in the device. One such type of memory device is a content addressable memory (CAM) device.
CAMs provide a rapid comparison between a specific pattern of received data bits, commonly known as a search key or comparand, and data values stored in an associative CAM memory array to provide a match/no-match result. If there is a match for every bit in a group of stored bits in selected CAM memory cells, with every corresponding bit in the comparand, a match flag via a match line indicates a match condition. In this way, the user is notified that the data in the comparand was found in memory and a value corresponding to the match is returned. Thus, the result is determined from finding a matching value (content), not from providing the address of the value as done for a Random Access Memory (RAM).
Generally, there are two types of CAM cells typically used in CAM arrays: binary CAM cells and ternary CAM or TCAM cells.
Binary CAM cells store either a logic high bit value or a logic low bit value. When the logic value stored in the binary CAM cell matches a data bit from an applied comparand, then that CAM cell provides a high impedance path to the match line and the match line is maintained at a logic high value (assuming all other CAM cells electrically connected to the CAM array row also match). In this way, a match is indicated. However, when the logic value stored in the binary CAM cell does not match the data bit from the applied comparand, then that CAM cell provides a low impedance path to ground to the match line and the match line is pulled low. In this way, it is indicated that a match has not occurred.
TCAM cells can store three bit values including a logic high value, a logic low value, and a “don't care” value. When storing logic high and logic low values, the TCAM cell operates like a binary CAM cell as described above. However, a TCAM cell storing a “don't care” value will provide a match condition for any data bit value from a comparand applied to that TCAM cell. This “don't care” capability allows CAM arrays to indicate when a data value matches a selected group of TCAM cells in a row of the CAM array. For example, assume each row of a TCAM array has eight TCAM cells. Additionally, assume that the first four TCAM cells of each row store one of a logic high and a logic low value (for comparison to the first four bits of an 8-bit comparand data value) and the last four TCAM cells of each row store “don't care” values. Under these conditions, when an 8-bit comparand data value is applied to the CAM array, a match occurs for each row of the CAM array in which the data values stored in the first four TCAM cells match the first four bits of the applied 8-bit comparand data value. An exemplary embodiment of an existing TCAM cell is set forth in FIG. 1 in a circuit schematic diagram and given the general reference character 100.
TCAM cell 100 includes a X-cell 110, a Y-cell 120, and a compare circuit 130. TCAM cell 100 has complementary bit lines (BLY and BLY_) as inputs to Y-cell 120, and complementary bit lines (BLX and BLX_) as inputs to X-cell 110. X-cell 110 and Y-cell 120 receive a word line WL as a common input. Compare circuit 130 receives complementary compare data (CD and CD_N) as inputs as well as receiving X-cell stored data and Y-cell stored data respectively at inputs (YD and XD). Compare circuit 130 provides a match output ML.
X-cell 110 and Y-cell 120 are essentially Static Random Access Memory (SRAM) cells having two inverters and two pass metal-oxide-semiconductor field effect transistors (MOSFETs). Compare circuit 130 has two serially connected MOSFETs providing the X-cell compare and two serially connected MOSFETs providing the Y-cell compare.